Tuesday, August 24, 2021

Next '19 Architecture Sessions | Forbes' Road to the Cloud (Cloud Next '19)

Aug. 24, 2021

Here is the link. 

In this session, we will demonstrate our approach to migrating to GCP. We will walk through our decision process for whether to utilize cloud-native tools versus building in-house solutions. Learn how best to prepare your workforce for this organizational and technological change, and what we learned from our process along the way. We will provide a blueprint for migrating media and publishing infrastructure to GCP with examples of the Forbes.com architecture before and after. The GCP migration was extremely important for our business, and Google has been a great partner along our journey to the cloud. Build with Google Cloud → https://bit.ly/2WQBZ0m Watch more: Next '19 Architecture Sessions here → https://bit.ly/Next19Architecture Next ‘19 All Sessions playlist → https://bit.ly/Next19AllSessions Subscribe to the GCP Channel → https://bit.ly/GCloudPlatform Speaker(s): William Anderson, Vadim Supitskiy Session ID: ARC202 product:Kubernetes Engine; event: Google Cloud Next 2019; re_ty: Publish; product: Cloud - General; fullname: William Anderson, Vadim Supitskiy; event: Google Cloud Next 2019;

Transforming to a Data Business - Dow Jones DNA (Cloud Next '19)

 Aug. 24, 2021

Here is the link. 

It is our hope that our lessons learned will spare other engineers restless nights tossing and turning over infrastructure considerations in transitioning to a data business. Dow Jones DNA (Data, News, and Analytics) platform was the answer to evolving customer requests to leverage premium news for text mining, machine learning, and AI solutions. This talk will detail our decisions made as we migrated our 30-year archive of big data to Google Cloud Storage and BigQuery. We will discuss the architecture trade-offs we faced in migrating 50 TB of historic data to the cloud as well as our ever-growing corpus ingesting 1.3 million articles daily. Dow Jones DNA required data migration, data processing ongoing at scale, and performance required in query responses. The DNA platform started with a team of two data engineers and grew to a team of five data engineers. Managed services were key in making the platform possible with a small team. We will detail the balance of real-world constraints such as small team size, performance versus cost, and the upper limits of quotas as our data ever expands. Build with Google Cloud → https://bit.ly/2KaUXgA Watch more: Next '19 Architecture Sessions here → https://bit.ly/Next19Architecture Next ‘19 All Sessions playlist → https://bit.ly/Next19AllSessions Subscribe to the GCP Channel → https://bit.ly/GCloudPlatform Speaker(s): Patricia Walsh, Dylan Roy Session ID: ARC204 product: Cloud - General; fullname: Patricia Walsh, Dylan Roy; event: Google Cloud Next 2019;


Breakfast and learn: Music Recommendations at Scale With Cloud Bigtable (Cloud Next '19)

Aug. 24, 2021

Here is the link. 

Spotify serves personalized music recommendations to hundreds of millions of happy customers worldwide, and powers a lot of this infrastructure with Google Cloud Bigtable. In this talk, we'll go into detail about how Cloud Bigtable allows us to deliver recommendations at scale, roll out experiments quickly, and ingest terabytes every day via Cloud Dataflow. We'll discuss a number of challenges we overcame when designing our recommendations infrastructure on top of Cloud Bigtable, including tips about how to design a good schema, how to avoid latency when ingesting new data, and effective caching strategies to scale to tens of millions of data points per second. We'll also discuss a number of challenges we overcame when architecting our recommendations infrastructure on top of Cloud Bigtable, including tips about how to design a good key space, how to avoid latency when ingesting new data, and how we built caching into every layer of our stack to scale to tens of millions of data points per second. Build with Google Cloud → https://bit.ly/2WN8356 Watch more: Next '19 Architecture Sessions here → https://bit.ly/Next19Architecture Next ‘19 All Sessions playlist → https://bit.ly/Next19AllSessions Subscribe to the GCP Channel → https://bit.ly/GCloudPlatform Speaker(s): Peter Sobot Session ID: ARC205 product:Cloud Bigtable, Cloud Dataflow; event: Google Cloud Next 2019; re_ty: Publish; product: Cloud - Databases - Cloud Bigtable; fullname: Peter Sobot;

Monday, August 23, 2021

RIG, GTE stock: Energy stocks on the rebound

Aug. 23, 2021

Here is the link. 

Crude was up more than 6 percent today as the commodity broke a 7-day losing streak. With CNBC's Melissa Lee and the Fast Money traders, Guy Adami, Dan Nathan, Tim Seymour and Brian Kelly. For access to live and exclusive video from CNBC subscribe to CNBC PRO: https://cnb.cx/2NGeIvi



RIG, GTE: Focus on micro, not macro trends: Goldman's Jeff Currie

Aug. 23, 2021

Here is the link.

Jeff Currie, Global Head of Commodities Research at Goldman Sachs, joins Closing Bell to discuss oil, gold and other commodities that may be affected by a Fed taper. For access to live and exclusive video from CNBC subscribe to CNBC PRO: https://cnb.cx/2NGeIvi

WTI crude 65.52 +3.38 [+5.44%]

Goldman Sachs on commodities: Focus on Micro, not Macro trends
Global head of commodity research

Goldman Sachs on commodities Q4 price targets
$90 BBL/Oil $10,620 T/COPPER

Past labor day - tight market, pullback, liquidity is low





Cloud Computing Market Projected To Reach $411B By 2020

 Oct 18, 2017,06:12pm EDT

Louis Columbus


Gartner’s latest worldwide public cloud services revenue forecast published earlier this month predicts Infrastructure-as-a-Service (IaaS), currently growing at a 23.31% Compound Annual Growth Rate (CAGR), will outpace the overall market growth of 13.38% through 2020. Software-as-a-Service (SaaS) revenue is predicted to grow from $58.6B in 2017 to $99.7B in 2020. Taking into account the entire forecast period of 2016 – 2020, SaaS is on pace to attain 15.65% compound annual growth throughout the forecast period, also outpacing the total cloud market. The following graphic compares revenue growth by cloud services category for the years 2016 through 2020. Please click on the graphic to expand it for easier reading.


Catalysts driving greater adoption and correspondingly higher CAGRs include a shift Gartner sees in infrastructure, middleware, application and business process services spending. In 2016, Gartner estimates approximately 17% of the total market revenue for these areas had shifted to the cloud. Gartner predicts by 2021, 28% of all IT spending will be for cloud-based infrastructure, middleware, application and business process services. Another factor is the adoption of Platform-as-a-Service (PaaS). Gartner notes that enterprises are confident that PaaS can be a secure, scalable application development platform in the future.  The following graphic compares the compound annual growth rates (CAGRs) of each cloud service area including the total market. Please click on the graphic to expand it for easier reading.




Book to read: Datacenter Design and Management: A Computer Architect's Perspective

 

Datacenter Design and Management: A Computer Architect's Perspective

Synthesis Lectures on Computer Architecture

Benjamin C. Lee
Duke University

Abstract

An era of big data demands datacenters, which house the computing infrastructure that translates raw data into valuable information. This book defines datacenters broadly, as large distributed systems that perform parallel computation for diverse users. These systems exist in multiple forms—private and public—and are built at multiple scales. Datacenter design and management is multifaceted, requiring the simultaneous pursuit of multiple objectives. Performance, efficiency, and fairness are first-order design and management objectives, which can each be viewed from several perspectives. This book surveys datacenter research from a computer architect's perspective, addressing challenges in applications, design, management, server simulation, and system simulation. This perspective complements the rich bodies of work in datacenters as a warehouse-scale system, which study the implications for infrastructure that encloses computing equipment, and in datacenters as distributed systems, which employ abstract details in processor and memory subsystems. This book is written for first- or second-year graduate students in computer architecture and may be helpful for those in computer systems. The goal of this book is to prepare computer architects for datacenter-oriented research by describing prevalent perspectives and the state-of-the-art.

Table of Contents: Preface / Acknowledgments / Introduction / Applications and Benchmarks / Design / Management / Hardware Simulation / System Simulation / Conclusions / Bibliography / Author's Biography

Edouard Bugnion | VMWare founder | a Swiss software architect and businessman

Edouard "Ed" Bugnion (born 1970) is a Swiss software architect and businessman.

Bugnion was raised in Neuchâtel, Switzerland.[1]

Bugnion graduated with a bachelor's degree in engineering from ETH Zurich in 1994 and a master's degree from Stanford University in 1996. He was one of the five founders of VMware in 1998 (with his advisor Mendel Rosenblum) and was the chief architect until 2004.[2] He had been a Ph.D. candidate in computer science at Stanford University prior to co-founding VMware. While he was chief architect, VMware developed the secure desktop initiative also known as NetTop for the US National Security Agency.[3] His primary research interests are in operating systems and computer architectures, and he was a key member of the SimOS and Disco virtual machine research teams.

After VMware, Bugnion was a founder of Nuova Systems which was funded by Cisco Systems, and acquired by them in April 2008.[4] Bugnion joined Cisco as vice president and chief technology officer of Cisco's Server Access and Virtualization Business Unit.[5] He promoted Cisco's Data Center 3.0 vision, and appeared in advertisements.[6] He resigned from Cisco in 2011 and resumed his PhD program of study at Stanford University, which he graduated from in 2012. In 2014, he became Adjunct Professor at the School of Computer Science at EPFL, Switzerland, where he is now the Vice President for Information Systems.[7]

Bugnion co-authored papers on operating systems and platform virtualization such as “Disco: Running Commodity Operating Systems on Scalable Multiprocessors,” in 1997.[8]

Bugnion is also an angel investor in startup companies such as Cumulus Networks.[9]

He was elected as an ACM Fellow in 2017.[10]

In 2020, Bugnion took a key role in fighting Covid19 through Exposure Notification, as a principal member of the team behind the concept and the implementation in Switzerland. He was also a member of the Swiss National COVID-19 Science Task Force 

Book to read: Hardware and Software Support for Virtualization

 

Hardware and Software Support for Virtualization

Synthesis Lectures on Computer Architecture

Edouard Bugnion
École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Jason Nieh
Columbia University
Dan Tsafrir
Technion -- Israel Institute of Technology

Abstract

This book focuses on the core question of the necessary architectural support provided by hardware to efficiently run virtual machines, and of the corresponding design of the hypervisors that run them. Virtualization is still possible when the instruction set architecture lacks such support, but the hypervisor remains more complex and must rely on additional techniques.

Despite the focus on architectural support in current architectures, some historical perspective is necessary to appropriately frame the problem. The first half of the book provides the historical perspective of the theoretical framework developed four decades ago by Popek and Goldberg. It also describes earlier systems that enabled virtualization despite the lack of architectural support in hardware.

As is often the case, theory defines a necessary—but not sufficient—set of features, and modern architectures are the result of the combination of the theoretical framework with insights derived from practical systems. The second half of the book describes state-of-the-art support for virtualization in both x86-64 and ARM processors. This book includes an in-depth description of the CPU, memory, and I/O virtualization of these two processor architectures, as well as case studies on the Linux/KVM, VMware, and Xen hypervisors. It concludes with a performance comparison of virtualization on current-generation x86- and ARM-based systems across multiple hypervisors.

Table of Contents: Preface / Acknowledgments / Definitions / The Popek/Goldberg Theorem / Virtualization without Architectural Support / x86-64: CPU Virtualization with VT-x / x86-64: MMU Virtualization with Extended Page Tables / x86-64: I/O Virtualization / Virtualization Support in ARM Processors / Comparing ARM and x86 Virtualization Performance / Bibliography / Authors' Biographies / Index

Natalie Enright Jerger | an American computer scientist | computer architecture and interconnection networks

 Natalie Enright Jerger is an American computer scientist known for research in computer science including computer architecture and interconnection networks.[1]

Education and career[edit]

Born in Plainfield, New Jersey, she attended Kent Place School[2] and received a BS in computer engineering from Purdue University in 2002.[3][4] She received an MS in Electrical Engineering from University of Wisconsin-Madison in 2004 and a PhD in Electrical Engineering from University of Wisconsin-Madison in 2008.

She joined the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto in 2009 as an Assistant Professor.[5] She was promoted to Associated Professor in 2014 and to Professor in 2017, becoming the Percy Edward Hart Professor of Electrical and Computer Engineering.[1][6] Enright Jerger co-chairs the ACM Council on Diversity and Inclusion.[7]

Book to read: On-Chip Networks: Second Edition | Plan to read in short future

 

Hardcover – June 19 2017

This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state of the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on-chip network research.

With the rapid advances in this field, we felt it was timely to update and review the state of the art in this second edition. We introduce two new chapters at the end of the book. We have updated the latest research of the past years throughout the book and also expanded our coverage of fundamental concepts to include several research ideas that have now made their way into products and, in our opinion, should be textbook concepts that all on-chip network practitioners should know. For example, these fundamental concepts include message passing, multicast routing, and bubble flow control schemes.

Book reading: Deep Learning for Computer Architects | Plan to read in short future

 

Deep Learning for Computer Architects

Synthesis Lectures on Computer Architecture

Brandon Reagen
Harvard University
Robert Adolf
Harvard University
Paul Whatmough
ARM Research and Harvard University
Gu-Yeon Wei
Harvard University
David Brooks
Harvard University

Abstract

Machine learning, and specifically deep learning, has been hugely disruptive in many fields of computer science. The success of deep learning techniques in solving notoriously difficult classification and regression problems has resulted in their rapid adoption in solving real-world problems. The emergence of deep learning is widely attributed to a virtuous cycle whereby fundamental advancements in training deeper models were enabled by the availability of massive datasets and high-performance computer hardware.

This text serves as a primer for computer architects in a new and rapidly evolving field. We review how machine learning has evolved since its inception in the 1960s and track the key developments leading up to the emergence of the powerful deep learning techniques that emerged in the last decade. Next we review representative workloads, including the most commonly used datasets and seminal networks across a variety of domains. In addition to discussing the workloads themselves, we also detail the most popular deep learning tools and show how aspiring practitioners can use the tools with the workloads to characterize and optimize DNNs.

The remainder of the book is dedicated to the design and optimization of hardware and architectures for machine learning. As high-performance hardware was so instrumental in the success of machine learning becoming a practical solution, this chapter recounts a variety of optimizations proposed recently to further improve future designs. Finally, we present a review of recent research published in the area as well as a taxonomy to help readers understand how various contributions fall in context.

Table of Contents: Preface / Introduction / Foundations of Deep Learning / Methods and Models / Neural Network Accelerator Optimization: A Case Study / A Literature Survey and Review / Conclusion / Bibliography / Authors' Biographies

Book reading: Architectural and Operating System Support for Virtual Memory

 

Architectural and Operating System Support for Virtual Memory

Publisher: Morgan & Claypool

Book Abstract:

This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space.

Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries.

However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today's systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or "big data" applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come.

Tor M. aamodt: UBC | Professor | GPU research

 

General-Purpose Graphics Processor Architectures

Synthesis Lectures on Computer Architecture

Tor M. Aamodt
University of British Columbia
Wilson Wai Lun Fung
Samsung Electronics
Timothy G. Rogers
Purdue University

Abstract

Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures.

The first chapter of this book describes the basic hardware structure of GPUs and provides a brief overview of their history. Chapter 2 provides a summary of GPU programming models relevant to the rest of the book. Chapter 3 explores the architecture of GPU compute cores. Chapter 4 explores the architecture of the GPU memory system. After describing the architecture of existing systems, Chapters \ref{ch03} and \ref{ch04} provide an overview of related research. Chapter 5 summarizes cross-cutting research impacting both the compute core and memory system.

This book should provide a valuable resource for those wishing to understand the architecture of graphics processor units (GPUs) used for acceleration of general-purpose applications and to those who want to obtain an introduction to the rapidly growing body of research exploring how to improve the architecture of these GPUs.

Table of Contents: Preface / Acknowledgments / Introduction / Programming Model / The SIMT Core: Instruction and Register Data Flow / Memory System / Crosscutting Research on GPU Computing Architectures / Bibliography / Authors' Biographies

Yale university: Principles of Secure Processor Architecture Design

 Aug. 23, 2021

Here is the link of slides. 

Slides and information available at: http://caslab.csl.yale.edu/tutorials/

Jakub Szefer: Book written | Yale professor

 BOOK

I am an author of a first book focusing specifically on design of secure processor architectures, including topics such as Trusted Execution Environments and Side-Channel Threats and Protections.

Jakub Szefer, "Principles of Secure Processor Architecture Design", Morgan & Claypool Publishers, October 2018.

The book's web page can be found here.

When I try to finish a book to read | Miracle happens | 55 yr old 11 years full time experience C#, Leetcode | Hackerrank gold medal winner

Aug. 23, 2021

Introduction

It is tough for me to correct myself, and I start to work on the change. One thing I start to work on is to go out and walk in weekend, shopping for grocery and other items, keep myself modern and observe how business runs in pandemic. I have this three month project to walk 9 KM to home, two hours project after work. The new challenge is to start to read books, watch Google I/O tech talks. Miracle happens. 

Book reading | Miracle happens

I do think that I need to be able to understand the technology books out there related to large distributed system, so I start to read a few books related to GFS, BigTable, and NoSQL etc. I found that it is super challenge. I need to spend a lot of time to read and then learn. 

I called it a miracle. I do think that life is gift after 55 year old. It is hard for me to maintain healthy weight, and I could not lower the weight below 190 lb after three months. I start to follow Google technologies and find time to work on more often, and I do need to learn how to spend less time on investing on stock market, and let market swing and bet on long term.